1. Field of the Invention
The present invention relates, generally, to a method of fabricating a high density printed circuit board (PCB), and more particularly, to a method of fabricating a high density PCB, which includes applying a strippable adhesive layer on a reinforced substrate (rigid substrate or carrier film) used as a base substrate, forming a metal foil on the adhesive layer by means of plating, laminating or sputtering, and forming a high density circuit on the formed metal foil serving as a seed layer using pattern plating.
2. Description of the Related Art
Were it not for software, a computer would be nothing but a hard metal box, as in the term ‘hardware’. Similarly, many ICs (Integrated Circuits) having superb performance and various electronic components would be useless, too, if they were aimlessly gathered.
Hence, in order to obtain electronic products operating in accordance with intended designs, the circuits and the components should be appropriately disposed, electrically connected to each other, and supplied with power. To this end, a PCB is used as a base substrate on which electronic components are mounted and electrically connected.
The term ‘PCB’ includes the word ‘printed’ because lines are formed using a screen printing process upon initial fabrication of the PCB.
Nowadays, although printing ink is sometimes used in a process of fabricating a single-sided PCB, a photosensitive film is applied to double-sided or other PCBs, for wiring. Thus, the term ‘PCB’ appears to be unsuitable. It is preferable that such a substrate be referred to as an electronic circuit board. The term ‘PCB’ is frequently used in Eastern Asia including Korea, whereas the term ‘printed wiring board (PWB)’ is frequently used in Europe and North America.
The PCB functions not only to electrically connect the electronic components but also to mechanically hold them. To increase the mechanical strength, the material constituting the PCB includes about 50% glass fiber as a reinforcing material.
Upon fabricating the PCB, since the material thereof is exposed to a high temperature of 200° C. or more, it should have heat resistance so as not to be bent or deformed.
Recently, while electronic devices are required to have high functionality and be light, slim, short and small, electronic components have been integrated and also mounted in high densities. Thus, a semiconductor package used for electronic devices has been increasingly miniaturized and the number of pins has increased.
Conventionally, a PCB called the PWB is mainly manufactured by patterning a copper foil layer of a copper-clad laminate (CCL) including a glass fiber epoxy laminate that is formed by incorporating an epoxy resin in a nonwoven fabric such as glass fiber and a copper foil layer clad on the glass fiber epoxy laminate, laminating a plurality of CCLs, forming a via hole through the laminated CCLs using a drill, and plating the wall surface of the via hole with copper so as to electrically connect the layers.
However, while the mounted components are required to be miniaturized and highly dense, the above PWB has a low wire density, hence causing problems in mounting the components.
In such circumstances, a build-up multilayer PWB has been recently used. The build-up multilayer PWB is formed by alternately stacking insulating layers formed only of a resin and conductors.
Further, the via hole is formed by use of laser, plasma, or photo methods, instead of conventional drilling, to have a small diameter. Such a via hole may be freely disposed, achieving a high density PCB.
As such, the interlayer connection is realized by means of a blind via hole or a buried via hole (a hole filled with a conductor). Among them, the buried via hole is receiving attention because it may form a stacked via hole because it enables a via hole to be formed on another via hole, thereby forming a stacked via hole.
In the buried via hole, any filling process using plating or conductive paste may be applied.
Meanwhile, the formation of the wire pattern includes, for example, a subtractive process for etching a copper foil, a semi-additive process using copper electroplating, a full-additive process using electroless copper plating, etc. Of these processes, the semi-additive process usable for a high wire density is worth noticing.
The process of etching the copper foil (subtractive process) includes attaching a photosensitive resist on a copper foil or a copper plated layer, photolithographically exposing and developing the photosensitive resist to form a resist pattern, removing unnecessary copper by etching, and removing the resist from the circuit.
FIGS. 1A to 1E are sectional views sequentially showing the fabrication of a high density PCB using a conventional subtractive process.
In FIG. 1A, a rigid substrate 101 serving as a base substrate is prepared. In FIG. 1B, an electroless copper plating process is carried out on the rigid substrate 101 used as a base substrate, to form an electroless copper plated layer 102. Subsequently, a copper electroplating process is performed on the electroless copper plated layer 102, to form a copper electroplated layer 103.
In FIG. 1C, an imaging process using a photosensitive material is performed on the copper electroplated layer 103, and thus, an etching resist 104 is patterned on the substrate.
In FIG. 1D, an etchant is sprayed to remove the copper foil, with the exception of the portion of the copper foil to be protected by the etching resist. In FIG. 1E, the etching resist, which is subsequently useless, is removed, to finally form a wire pattern of a copper foil.
In the subtractive process, the ability of forming fine circuits relies on the thickness of copper and resolution of the resist. Since the subtractive process uses a copper etching mechanism, an aspect ratio of about 2.0 to the copper thickness may be obtained. Hence, when the copper thickness is 10 μm, L/S (line and space width) is limited to 20/20 μm.
FIGS. 2A to 2E are sectional views sequentially showing the fabrication of a high density PCB using a conventional semi-additive process.
In FIG. 2A, to fabricate the high density PCB using a semi-additive process, a rigid substrate 201 serving as a base substrate is first prepared.
In FIG. 2B, an electroless copper plating process is performed on the base substrate, to form a thin seed layer 202.
In FIG. 2C, a dry film 203 is laminated on the thin seed layer 202 formed by electroless copper plating, and exposed and developed, to form a wire pattern.
In FIG. 2D, on the wire pattern formed on the thin seed layer 202 that is electroless copper plated, a copper electroplated layer 204 is formed using a copper electroplating process, thus completing the wire pattern of the copper foil.
In FIGS. 2E and 2F, the dry film 203 and the seed layer 202 are sequentially removed, to complete a desired circuit pattern.
As for the semi-additive process, since the residue of the seed layer or the circuit width may be over-etched upon etching the electroless copper seed layer, L/S is limited to 15/15 μm.
FIGS. 3A to 3D are sectional views sequentially showing the fabrication of a high density PCB using a conventional full-additive process.
In FIG. 3A, to fabricate the high density PCB using a full-additive process, an insulating resin substrate 301 serving as a base substrate is first prepared.
In FIG. 3B, a photosensitive resist 302 is attached to the surface of the insulating resin substrate 301, and exposed and developed, to form a resist pattern.
In FIG. 3C, an electroless copper plating process is performed on the wire pattern formed by the photosensitive resist 302, to form an electroless copper plated layer 303.
Then, in FIG. 3D, the photosensitive resist 302 is removed to complete a circuit.
As for the full-additive process, the ability of forming fine circuits relies on the resolution of the resist and the thickness of the copper deposited by electroless plating, and L/S is limited to 15/15 μm.
In the case where the circuit is formed using the subtractive process, side etching by the etchant may occur and negatively affects the formation of finer circuits. Thus, respective PCB manufacturers have used a semi-additive process.
In the semi-additive process, however, limitations are imposed on the manifestation of sufficient performance of the resist and the formation of fine circuits, attributable to the adhesion of the resist and the adhesion of the copper circuit exclusively depending on the material of the insulating layer and the state of the adhering surface upon forming the fine lines.
Further, seed etching for use in etching the copper seed layer formed by electroless plating or sputtering negatively affects the fineness of circuits. That is, the seed etching may etch the circuit, as well as the seed layer. Thus, upon pattern plating, the thickness of the plated layer and the line width are corrected to be large.
Due to the correction, it is difficult to realize the fine circuits. In seed etching, the etchant may infiltrate the copper circuit, and the circuit may become loose. In addition, insufficient seed etching causes the seed layer to remain, leading to short-circuit problems. Such problems become significant as the intervals between circuits decrease.
Japanese Patent Laid-open Publication No. 2004-63575, aiming at increasing the area of a copper pad to be mounted, using a single-sided CCL, forming a circuit by a subtractive process, and etching a resin, is quite different from the present invention. Further, the above patent is unsuitable for use in the fabrication of high density PCBs, since the circuits are formed using the subtractive process.
Japanese Patent Laid-open Publication Nos. 2002-335079, 2003-51676, 2003-168867, 2003-218524, 2003-218532, 2003-234577, 2003-289182, and 2004-6687 disclose a method of forming a circuit. These patents, concerning the removal of a metal sheet or a metal foil, which is used as a current application portion, by etching, are different from the present invention in which a strippable layer is stripped.
Japanese Patent Laid-open Publication No. 2004-071821 discloses a method of forming a circuit, including forming a copper foil on an adhesive layer, forming the copper foil into a circuit using a subtractive process, and transferring the circuit to an insulating substrate. However, this patent is disadvantageous because fine circuits cannot be formed using the subtractive process.
On the other hand, a wire transferring method using a semi-additive process makes free circuit design possible, and thus, is used to form multilayer PCBs by a collective lamination process. The wire transferring method using the semi-additive process includes forming an insulating resin layer on the wire-forming surface of a conductive frame. As such, to ensure the adhesion between the wire surface and the insulating resin layer, heat treatment is performed.
Since the heat treatment requires a high temperature of 200° C. or more, such heat hysteresis induces mutual diffusion between copper used for the conductive frame and gold used as a barrier metal, thereby forming an alloy layer. Accordingly, after the conductive frame is removed, the copper-gold alloy is exposed, resulting in a flip chip that is poorly bonded to the gold stud bump or weak adhesion of a soldering adhesive upon soldering, reduced reliability of the bonded portion, reduced mounting reliability, and high product defect rates.
To solve the problems, Japanese Patent Laid-open Publication No. 2004-47898 discloses a method of fabricating a PWB and a method of fabricating a multilayer PWB, in which the above methods includes forming a metal diffusion prevention layer to manufacture a high density substrate.
However, the methods of fabricating a PWB and a multilayer PWB disclosed in Japanese Patent Laid-open Publication No. 2004-47898 are disadvantageous because too long a time is required to remove the conductive frame by etching.
That is, in the methods of fabricating a PWB and a multilayer PWB disclosed in Japanese Patent Laid-open Publication No. 2004-47898, a first etching and a second etching for selective etching using sulfric acid (H2SO4) are performed to remove a nickel (Ni) board used as a conductive frame. As such, the first etching and the second etching require 1320 sec and 3600 sec, respectively, and the total etching time amounts to 4920 sec, which is about 1.5 hr. Hence, the above patent is difficult to put to practical use.
Specifically, in the methods of fabricating a PWB and a multilayer PWB disclosed in Japanese Patent Laid-open Publication No. 2004-47898, the nickel board used as a conductive frame is about 200 μm thick.
The first etching is performed under conditions of a temperature of 30-37.6° C., a spray pressure of 0.1 MPa, a chamber length of 1.3 m, and a conveyor speed of 0.65 m/min, using a solution including 20% H2NO3 and 1.75% H2O2.
The first etching under the above conditions is carried out 11 times at an etching rate of 7-8 μm/min, thus requiring 1320 sec.
Then, the second etching, which is used to selectively etch only the nickel board, is performed under conditions of a temperature of 25.0-27.5° C., a spray pressure of 0.1 MPa, a chamber length of 1.3 m, and a conveyor speed of 0.65 m/min, using a solution including 10% H2SO4 and 1.75% H2O2.
The second etching under the above conditions is conducted 30 times at an etching rate of 1.0-2.0 μm/min, thus requiring 3600 sec.
In this way, the etching process including the first etching and the second etching requires 4920 sec, which is about 1.5 hr. Thus, it is difficult to actually manufacture products using the above technique.